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Posts Tagged ‘VU.CS302-. Digital. Logic .Design .(Session – 1). MIDTERM .EXAMINATION .Spring.2009’

VU CS302- Digital Logic Design (Session – 1) MIDTERM EXAMINATION Spring 2009

.

MIDTERM EXAMINATION

Spring 2009

CS302- Digital Logic Design (Session – 1)

Question No: 1 ( Marks: 1 ) – Please choose one

In

the binary number “10011” the weight of the most significant digit is ____

► 24 (2 raise to power 4)

► 23 (2 raise to power 3)

► 20 (2 raise to power 0)

► 21 (2 raise to power 1)

Question No: 2 ( Marks: 1 ) – Please choose one

An

S-R latch can be implemented by using _________ gates

► AND, OR

► NAND, NOR

► NAND, XOR

► NOT, XOR

Question No: 3 ( Marks: 1 ) – Please choose one

A

latch has _____ stable states

► One

► Two

► Three

► Four

Question No: 4 ( Marks: 1 ) – Please choose one

Sequential circuits have storage elements

► True

► False

Question No: 5 ( Marks: 1 ) – Please choose one

The

ABEL symbol for “XOR” operation is

► $

► #

.

► !

► &

Question No: 6 ( Marks: 1 ) – Please choose one

A

Demultiplexer is not available commercially.

► True

► False

Question No: 7 ( Marks: 1 ) – Please choose one

Using multiplexer as parallel to serial converter requires ___________ connected to the

multiplexer

► A parallel to serial converter circuit

► A counter circuit

► A BCD to Decimal decoder

► A 2-to-8 bit decoder

Question No: 8 ( Marks: 1 ) – Please choose one

The

device shown here is most likely a

► Comparator

► Multiplexer

► Demultiplexer

► Parity generator

Question No: 9 ( Marks: 1 ) – Please choose one

The

main use of the Multiplexer is to

► Select data from multiple sources and to route it to a single Destination

► Select data from Single source and to route it to a multiple Destinations

.

► Select data from Single source and to route to single destination

► Select data from multiple sources and to route to multiple destinations

Question No: 10 ( Marks: 1 ) – Please choose one

A

logic circuit with an output consists of ________.

► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter

► two AND gates, one OR gate, two inverters

► two AND gates, one OR gate

Question No: 11 ( Marks: 1 ) – Please choose one

The

binary value of 1010 is converted to the product term

► True

► False

Question No: 12 ( Marks: 1 ) – Please choose one

The

3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

► 16

Question No: 13 ( Marks: 1 ) – Please choose one

Following is standard POS expression

► True

► False

Question No: 14 ( Marks: 1 ) – Please choose one

.

The

output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the

symbol’+’ here represents OR Gate.

► Undefined

► One

► Zero

► 10 (binary)

Question No: 15 ( Marks: 1 ) – Please choose one

The

Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code

► 2-bit

► 7-bit

► 8-bit

► 16-bit

Question No: 16 ( Marks: 1 ) – Please choose one

The

diagram given below represents __________

► Demorgans law

► Associative law

► Product of sum form

► Sum of product form

Question No: 17 ( Marks: 1 )

How can a PLD be programmed?

Question No: 18 ( Marks: 1 )

How many input and output bits do a Half-Adder contain?

Question No: 19 ( Marks: 2 )

.

Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?

Question No: 20 ( Marks: 3 )

Name the three declarations that are included in “declaration section” of the

module that is created when an Input (source) file is created in ABEL.

Question No: 21 ( Marks: 5 )

Explain with example how noise affects Operation of a CMOS AND Gate circuit.

Question No: 22 ( Marks: 10 )

explain the SOP based implementation of the Adjacent 1s Detector Circuit

VU CS302- Digital Logic Design (Session – 1) MIDTERM EXAMINATION Spring 2009

.

MIDTERM EXAMINATION

Spring 2009

CS302- Digital Logic Design (Session – 1)

Question No: 1 ( Marks: 1 ) – Please choose one

GAL

can be reprogrammed because instead of fuses _______ logic is used in it

► E2CMOS

► TTL

► CMOS+

► None of the given options

Question No: 2 ( Marks: 1 ) – Please choose one

The

device shown here is most likely a

► Comparator

► Multiplexer

► Demultiplexer

► Parity generator

Question No: 3 ( Marks: 1 ) – Please choose one

If

“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

► 2nd

► 4th

► 14th

► No output wire will be activated

Question No: 4 ( Marks: 1 ) – Please choose one

Half-Adder Logic circuit contains 2 XOR Gates

► True

► False

Question No: 5 ( Marks: 1 ) – Please choose one

.

A

particular Full Adder has ► 3 inputs and 2 output

► 3 inputs and 3 output

► 2 inputs and 3 output

► 2 inputs and 2 output

Question No: 6 ( Marks: 1 ) – Please choose one

Sum  A BC

CarryOut  C(A B)  AB

are the Sum and CarryOut expression of

► Half Adder

► Full Adder

► 3-bit parralel adder

► MSI adder cicuit

Question No: 7 ( Marks: 1 ) – Please choose one

A

Karnaugh map is similar to a truth table because it presents all the possible values of input

variables and the resulting output of each value.

► True

► False

Question No: 8 ( Marks: 1 ) – Please choose one

The

output A < B is set to 1 when the input combinations is __________

► A=10, B=01

► A=11, B=01

► A =01, B=01 ► A=01, B=10

Question No: 9 ( Marks: 1 ) – Please choose one

The

4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 1 2 ► 16

.

Question No: 10 ( Marks: 1 ) – Please choose one

Generally, the Power dissipation of _______ devices remains constant throughout their operation.

► TTL

► CMOS 3.5 series

► CMOS 5 Series

► Power dissipation of all circuits increases with time.

Question No: 11 ( Marks: 1 ) – Please choose one

The

decimal “8” is represented as _________ using Gray-Code.

► 0 011 ► 1100

► 1000

► 1010

Question No: 12 ( Marks: 1 ) – Please choose one

(A+B).(A+C) = ___________

► B +C ► A+BC

► AB+C

► AC+B

Question No: 13 ( Marks: 1 ) – Please choose one

A.(B

+ C) = A.B + A.C is the expression of _________________

► Demorgan’s Law

► Commutative Law

► Distributive Law

► Associative Law

Question No: 14 ( Marks: 1 ) – Please choose one

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

FALSE

► TRUE

.

Question No: 15 ( Marks: 1 ) – Please choose one

In

ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits

► 8-bits

► 16-bits

► 32-bits

► 64-bits

Question No: 16 ( Marks: 1 ) – Please choose one

Caveman number system is Base _5_____ number system

► 2 ► 5

► 10

► 16

Question No: 17 ( Marks: 1 )

Briefly state the basic principle of Repeated Multiplication-by-2 Method.

Question No: 18 ( Marks: 1 )

How

standard Boolean expressions can be converted into truth table format.

Question No: 19 ( Marks: 2 )

What will be the out put of the diagram given below

Question No: 20 ( Marks: 3 )

.

When an Input (source) file is created in ABEL a module is created which has three sections. Name

These three sections.

Question No: 21 ( Marks: 5 )

Explain “AND” Gate and some of its uses

Question No: 22 ( Marks: 10 )

Write down different situations where we need the sequential circuits.

VU CS302- Digital Logic Design (Session – 1)MIDTERM EXAMINATION Spring 2009

.

MIDTERM EXAMINATION

Spring 2009

CS302- Digital Logic Design (Session – 1)

Question No: 1 ( Marks: 1 ) – Please choose one

GAL

can be reprogrammed because instead of fuses _______ logic is used in it

► E2CMOS

► TTL

► CMOS+

► None of the given options

Question No: 2 ( Marks: 1 ) – Please choose one

The

device shown here is most likely a

► Comparator

► Multiplexer

► Demultiplexer

► Parity generator

Question No: 3 ( Marks: 1 ) – Please choose one

If

“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

► 2nd

► 4th

► 14th

► No output wire will be activated

Question No: 4 ( Marks: 1 ) – Please choose one

Half-Adder Logic circuit contains 2 XOR Gates

► True

► False

Question No: 5 ( Marks: 1 ) – Please choose one

A

.

particular Full Adder has ► 3 inputs and 2 output

► 3 inputs and 3 output

► 2 inputs and 3 output

► 2 inputs and 2 output

Question No: 6 ( Marks: 1 ) – Please choose one

Sum  A BC

CarryOut  C(A B)  AB

are the Sum and CarryOut expression of

► Half Adder

► Full Adder

► 3-bit parralel adder

► MSI adder cicuit

Question No: 7 ( Marks: 1 ) – Please choose one

A

Karnaugh map is similar to a truth table because it presents all the possible values of input

variables and the resulting output of each value.

► True

► False

Question No: 8 ( Marks: 1 ) – Please choose one

The

output A < B is set to 1 when the input combinations is __________

► A=10, B=01

► A=11, B=01

► A =01, B=01 ► A=01, B=10

Question No: 9 ( Marks: 1 ) – Please choose one

The

4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 1 2 ► 16

Question No: 10 ( Marks: 1 ) – Please choose one

.

Generally, the Power dissipation of _______ devices remains constant throughout their operation.

► TTL

► CMOS 3.5 series

► CMOS 5 Series

► Power dissipation of all circuits increases with time.

Question No: 11 ( Marks: 1 ) – Please choose one

The

decimal “8” is represented as _________ using Gray-Code.

► 0 011 ► 1100

► 1000

► 1010

Question No: 12 ( Marks: 1 ) – Please choose one

(A+B).(A+C) = ___________

► B +C ► A+BC

► AB+C

► AC+B

Question No: 13 ( Marks: 1 ) – Please choose one

A.(B

+ C) = A.B + A.C is the expression of _________________

► Demorgan’s Law

► Commutative Law

► Distributive Law

► Associative Law

Question No: 14 ( Marks: 1 ) – Please choose one

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

FALSE

► TRUE

Question No: 15 ( Marks: 1 ) – Please choose one

.

In

ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits

► 8-bits

► 16-bits

► 32-bits

► 64-bits

Question No: 16 ( Marks: 1 ) – Please choose one

Caveman number system is Base _5_____ number system

► 2 ► 5

► 10

► 16

Question No: 17 ( Marks: 1 )

Briefly state the basic principle of Repeated Multiplication-by-2 Method.

Question No: 18 ( Marks: 1 )

How

standard Boolean expressions can be converted into truth table format.

Question No: 19 ( Marks: 2 )

What will be the out put of the diagram given below

Question No: 20 ( Marks: 3 )

.

When an Input (source) file is created in ABEL a module is created which has three sections. Name

These three sections.

Question No: 21 ( Marks: 5 )

Explain “AND” Gate and some of its uses

Question No: 22 ( Marks: 10 )

Write down different situations where we need the sequential circuits.

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