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Posts Tagged ‘VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010’

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

 MIDTERM EXAMINATION

CS302- Digital Logic Design (Session – 2

Question No: 1 ( Marks: 1 ) – Please choose one

Which of the number is not a representative of hexadecimal system

► 1234

► ABCD

► 1001

► DEFH

Question No: 2 ( Marks: 1 ) – Please choose one

The Unsigned Binary representation can only represent positive binary numbers

► True

► False

Question No: 3 ( Marks: 1 ) – Please choose one

The values that exceed the specified range can not be correctly represented and are considered as

________

► Overflow

► Carry

► Parity

► Sign value

Question No: 4 ( Marks: 1 ) – Please choose one

The 4-bit 2’s complement representation of “-7” is _____________

► 0111

► 1111

► 1001

► 0110

L-2

Question No: 5 ( Marks: 1 ) – Please choose one

AB  ABC  AC is an example of ________

► Product of sum form

► Sum of product form

► Demorgans law

► Associative law

Question No: 6 ( Marks: 1 ) – Please choose one

The diagram given below represents __________

► Demorgans law

► Associative law

► Product of sum form

► Sum of product form

Question No: 7 ( Marks: 1 ) – Please choose one

The output of an AND gate is one when _______

► All of the inputs are one

► Any of the input is one

► Any of the input is zero

► All the inputs are zero

Question No: 8 ( Marks: 1 ) – Please choose one

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

► 16

Question No: 9 ( Marks: 1 ) – Please choose one

A BCD to 7-Segment decoder has

► 3 inputs and 7 outputs

► 4 inputs and 7 outputs

► 7 inputs and 3 outputs

► 7 inputs and 4 outputs

Question No: 10 ( Marks: 1 ) – Please choose one

Two 2-input, 4-bit multiplexers 74X157 can be connected to implement a ____ multiplexer.

► 4-input, 8-bit

► 4-input, 16-bit

► 2-input, 8-bit

► 2-input, 4-bit

Question No: 11 ( Marks: 1 ) – Please choose one

The PROM

consists of a fixed non-programmable ____________ Gate array configured as a decoder.

► AND

► OR

► NOT

► XOR

Question No: 12 ( Marks: 1 ) – Please choose one

In ABEL the variable ‘A’ is treated separately from variable ‘a’

► True

► False

Question No: 13 ( Marks: 1 ) – Please choose one

The ABEL notation equivalent to Boolean expression A+B is:

► A & B

► A ! B

► A # B

► A $ B

L-21

Question No: 14 ( Marks: 1 ) – Please choose one

If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input

goes to 0, the latch will be ________.

► SET

► RESET

► Clear

► Invalid

Question No: 15 ( Marks: 1 ) – Please choose one

Demultiplexer has

► Single input and single outputs.

► Multiple inputs and multiple outputs.

► Single input and multiple outputs.

► Multiple inputs and single output.

Question No: 16 ( Marks: 1 ) – Please choose one

Which one is true:

► Power consumption of TTL is higher than of CMOS

► Power consumption of CMOS is higher than of TTL

► Both TTL and CMOS have same power consumption

► Power consumption of both CMOS and TTL depends on no. of gates in the circuit.

Question No: 17 ( Marks: 1 )

Briefly state the basic principle of Repeated Division-by-2 method.

Repeated Division-by-2

Repeated Division-by-2 method allows decimal numbers of any magnitude to be

converted into binary. In this method the Decimal number to be converted into its Binary

equivalent is repeatedly divided by 2. The divisor is selected as 2 because the decimal

number is being converted into Binary a Base-2 Number system. Repeated division

method can be used to convert decimal number into any Number system by repeated

division by the Base-Number. For example, the decimal number can be converted into

the Caveman Number system by repeatedly dividing by 5, the Base number of the

Caveman Number System. The Repeated Division method will be used in latter lectures

to convert decimal into Hexadecimal and Octal Number Systems.

In the Repeated-Division method the Decimal number to be converted is divided

by the Base Number, in this particular case 2. A quotient value and a remainder value is

generated, both values are noted done. The remainder value in all subsequent divisions

would be either a 0 or a 1. The quotient value obtained as a result of division by 2 is

divided again by 2. The new quotient and remainder values are again noted down. In each

step of the repeated division method the remainder values are noted down and the

quotient values are repeatedly divided by the base number. The process of repeated

division stops when the quotient value becomes zero. The remainders that have been

noted in consecutive steps are written out to indicate the Binary equivalent of the Original

Decimal Number.

Question No: 18 ( Marks: 1 )

Briefly state the basic principle of Repeated Multiplication-by-2 Method.

Repeated Multiplication-by-2 Method

An alternate to the Sum-of-Weights method used to convert Decimal fractions to

equivalent Binary fractions is the repeated multiplication by 2 method. In this method the

number to be converted is repeatedly multiplied by the Base Number to which the

number is being converted to, in this case 2. A new number having an Integer part and a

Fraction part is generated after each multiplication. The Integer part is noted down and

the fraction part is again multiplied with the Base number 2. The process is repeated until

the fraction term becomes equal to zero.

Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to be

easily converted into binary. The conversion of Decimal fraction 0.625 into Binary

equivalent using the Repeated Multiplication-by-2 method is illustrated in a tabular form.

Table 2.4. Reading the Integer column from bottom to top and placing a decimal point in

the left most position gives 0.101 the binary equivalent of decimal fraction 0.625

Question No: 19 ( Marks: 2 )

Draw the circuit diagram of a Tri-State buffer.

Question No: 20 ( Marks: 3 )

Add -13 and +7 by converting them in binary system your result must be in binary.

Question No: 21 ( Marks: 5 )

Explain “Sum of Weights” method with example for “Octal to Decimal” conversion

1. Sum-of-Weights Method

Sum-of-weights as the name indicates sums the weights of the Binary Digits (bits)

of a Binary Number which is to be represented in Decimal. The Sum-of-Weights method

can be used to convert a Binary number of any magnitude to its equivalent Decimal

representation.

In the Sum-of-Weights method an extended expression is written in terms of the

Binary Base Number 2 and the weights of the Binary number to be converted. The

weights correspond to each of the binary bits which are multiplied by the corresponding

binary value. Binary bits having the value 0 do not contribute any value towards the final

sum expression.

The Binary number 101102 is therefore written in the form of an expression

having weights 20 ,21,22 ,23 AND 24 corresponding to the bits 0, 1, 1, 0 and 1 respectively.

Weights 20AND 23 do not contribute in the final sum as the binary bits corresponding to

these weights have the value 0.

101102 = 1 x 24  0 x 23  1 x 22  1 x 21  0 x 20

= 16 + 0 + 4 + 2 + 0

= 22

Question No: 22 ( Marks: 10 )

Explain the Implementation of an Odd-Parity Generator Circuit i.e by drawing function table, maping it to K-map and then simplifying the expression.

MIDTERM EXAMINATION

CS302- Digital Logic Design

Question No: 1 ( Marks: 1 ) – Please choose one

GAL can be reprogrammed because instead of fuses _______ logic is used in it

E2CMOS

► TTL

► CMOS+

► None of the given options

Question No: 2 ( Marks: 1 ) – Please choose one

The device shown here is most likely a

► Comparator

Multiplexer

► Demultiplexer

► Parity generator

Question No: 3 ( Marks: 1 ) – Please choose one

If “1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

► 2nd

► 4th

► 14th

No output wire will be activated

Question No: 4 ( Marks: 1 ) – Please choose one

Half-Adder Logic circuit contains 2 XOR Gates

► True

False

Question No: 5 ( Marks: 1 ) – Please choose one

A particular Full Adder has

3 inputs and 2 output

► 3 inputs and 3 output

► 2 inputs and 3 output

► 2 inputs and 2 output

Question No: 6 ( Marks: 1 ) – Please choose one

Sum  A BC

CarryOut  C(A B)  AB

are the Sum and CarryOut expression of

► Half Adder

Full Adder

► 3-bit parralel adder

► MSI adder cicuit

Question No: 7 ( Marks: 1 ) – Please choose one

A Karnaugh map is similar to a truth table because it presents all the possible values of

input variables and the resulting output of each value.

True

► False

Question No: 8 ( Marks: 1 ) – Please choose one

The output A < B is set to 1 when the input combinations is __________

► A=10, B=01

► A=11, B=01

► A=01, B=01

A=01, B=10

Here output combination should A < B

Question No: 9 ( Marks: 1 ) – Please choose one

The 4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12

16

Question No: 10 ( Marks: 1 ) – Please choose one

Generally, the Power dissipation of _______ devices remains constant throughout their

operation.

TTL

► CMOS 3.5 series

► CMOS 5 Series

► Power dissipation of all circuits increases with time.

Question No: 11 ( Marks: 1 ) – Please choose one

The decimal “8” is represented as _________ using Gray-Code.

► 0011

  1100

► 1000

► 1010

Question No: 12 ( Marks: 1 ) – Please choose one

(A+B).(A+C) = ___________

► B+C

A+BC

► AB+C

► AC+B

Question No: 13 ( Marks: 1 ) – Please choose one

A.(B + C) = A.B + A.C is the expression of _________________

► Demorgan’s Law

► Commutative Law

Distributive Law

► Associative Law

Question No: 14 ( Marks: 1 ) – Please choose one

NOR Gate can be used to perform the operation of AND, OR and NOT Gate

FALSE

► TRUE

Question No: 15 ( Marks: 1 ) – Please choose one

In ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits

► 8-bits

► 16-bits

32-bits

► 64-bits

Question No: 16 ( Marks: 1 ) – Please choose one

Caveman number system is Base _5_____ number system

► 2

5

► 10

► 16

Question No: 17 ( Marks: 1 )

Briefly state the basic principle of Repeated Multiplication-by-2 Method.

Repeated Multiplication-by-2 method allows decimal fractions of any magnitude to

be easily converted into binary.

Question No: 18 ( Marks: 1 )

How standard Boolean expressions can be converted into truth table format.

Standard Boolean expressions can be converted into truth table format using binary

values for each term in the expression. Standard SOP or POS expressions can

also be determined from a truth table.

Question No: 19 ( Marks: 2 )

What will be the out put of the diagram given below

A.B + A.B.C.D

Question No: 20 ( Marks: 3 )

When an Input (source) file is created in ABEL a module is created which has three

sections. Name These three sections.

Answer:

The three sections are:

• Boolean Equations

• Truth Tables

• State Diagrams

Question No: 21 ( Marks: 5 )

Explain “AND” Gate and some of its uses

AND gates are used to combine multiple signals, if all the signals are TRUE then the

output will also be TRUE. If any of the signals are FALSE, then the output will be

false. ANDs aren’t used as much as NAND gates; NAND gates use less components

and have the advantage that they be used as an inverter.

Question No: 22 ( Marks: 10 )

Write down different situations where we need the sequential circuits.

Digital circuits that use memory elements for their operation are known as

Sequential circuits. Thus Sequential circuits are implemented by combining

combinational circuits with memory elements.

 

 

 

Question No: 1 ( Marks: 1 ) – Please choose one

In the binary number “10011” the weight of the most significant digit is ____

24 (2 raise to power 4)

► 23 (2 raise to power 3)

► 20 (2 raise to power 0)

► 21 (2 raise to power 1)

Question No: 2 ( Marks: 1 ) – Please choose one

An S-R latch can be implemented by using _________ gates

► AND, OR

NAND, NOR

► NAND, XOR

► NOT, XOR

Question No: 3 ( Marks: 1 ) – Please choose one

A latch has _____ stable states

► One

Two

► Three

► Four

Question No: 4 ( Marks: 1 ) – Please choose one

Sequential circuits have storage elements

True

► False

Question No: 5 ( Marks: 1 ) – Please choose one

The ABEL symbol for “XOR” operation is

$

► #

► !

► &

Question No: 6 ( Marks: 1 ) – Please choose one

A Demultiplexer is not available commercially.

True

► False

Question No: 7 ( Marks: 1 ) – Please choose one

Using multiplexer as parallel to serial converter requires ___________ connected to the

multiplexer

► A parallel to serial converter circuit

A counter circuit

► A BCD to Decimal decoder

► A 2-to-8 bit decoder

Question No: 8 ( Marks: 1 ) – Please choose one

The device shown here is most likely a

► Comparator

Multiplexer

► Demultiplexer

► Parity generator

Question No: 9 ( Marks: 1 ) – Please choose one

The main use of the Multiplexer is to

Select data from multiple sources and to route it to a single

Destination

► Select data from Single source and to route it to a multiple Destinations

► Select data from Single source and to route to single destination

► Select data from multiple sources and to route to multiple destinations

Question No: 10 ( Marks: 1 ) – Please choose one

A logic circuit with an output consists of ________.

► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter

two AND gates, one OR gate, two inverters

► two AND gates, one OR gate

Question No: 11 ( Marks: 1 ) – Please choose one

The binary value of 1010 is converted to the product term

► True

False

Question No: 12 ( Marks: 1 ) – Please choose one

The 3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

8

► 12

► 16

Question No: 13 ( Marks: 1 ) – Please choose one

Following is standard POS expression

True

► False

Question No: 14 ( Marks: 1 ) – Please choose one

The output of the expression F=A+B+C will be Logic ________ when A=0, B=1,

C=1. the symbol’+’ here represents OR Gate.

► Undefined

One

► Zero

► 10 (binary)

Question No: 15 ( Marks: 1 ) – Please choose one

The Extended ASCII Code (American Standard Code for Information Interchange) is a

_____ code

► 2-bit

7-bit

► 8-bit

► 16-bit

Question No: 16 ( Marks: 1 ) – Please choose one

The diagram given below represents __________

► Demorgans law

► Associative law

Product of sum form

► Sum of product form

Question No: 17 ( Marks: 1 )

How can a PLD be programmed?

PLDs are programmed with the help of computer which runs the programming

software. The computer is connected to a programmer socket in which the PLD is

inserted for programming. PLDs can also be programmed when they are installed

on a circuit board

Question No: 18 ( Marks: 1 )

How many input and output bits do a Half-Adder contain?

The Half-Adder has a 2-bit input and a 2-bit output.

Question No: 19 ( Marks: 2 )

Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?

The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder

described earlier figure 16.9. The only difference between the two is the addition

of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit

figure

Question No: 20 ( Marks: 3 )

Name the three declarations that are included in “declaration section” of

the module that is created when an Input (source) file is created in ABEL.

Device declaration, pin declarations and set declarations.

Question No: 21 ( Marks: 5 )

Explain with example how noise affects Operation of a CMOS AND Gate circuit.

Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first

AND gate has both its inputs connected to logic high, therefore the output of the

gate is guaranteed to be logic high. The logic high voltage output of the first AND

gate is assumed to be 4.6 volts well within the valid VOH range of 5-4.4 volts.

Assume the same noise signal (as described earlier) is added to the output signal

of the first AND gate.

Question No: 22 ( Marks: 10 )

explain the SOP based implementation of the Adjacent 1s Detector Circuit

The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in

the

input, the output is set to high. The operation of the Adjacent 1s Detector is

represented by the

function table. Table 13.6. In the function table, for the input combinations 0011,

0110, 0111,

1011, 1100, 1101, 1110 and 1111 the output function is a 1.

Implementing the circuit directly from the function table based on the SOP form

requires 8 AND gates for the 8 product terms (minterms) with an 8-input OR gate.

Figure 13.3.

The total gate count is

• One 8 input OR gate

• Eight 4 input AND gates

• Ten NOT gates

The expression can be simplified using a Karnaugh map, figure 13.4, and then the

simplified expression can be implemented to reduce the gate count. The

simplified expression

isAB + CD +BC . The circuit implemented using the expression AB + CD +BC

has reduced

to 3 input OR gate and 2 input AND gates.

The simplified Adjacent 1s Detector circuit uses only four gates reducing the cost,

the

size of the circuit and the power requirement. The propagation delay of the circuit

is of the order of two gates

.

:13cO�r’<�i `o e=’font-family:”Times New Roman”; border:none windowtext 1.0pt;mso-border-alt:none windowtext 0in;padding:0in’>   Question No: 26    ( Marks: 1 )    – Please choose one

 

 The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2)

► 2n   (n multiplied by 2)

► 2n   (2 raise to power n)

► n  (n raise to power 2)

Question No: 27    ( Marks: 2 )

 Draw the Truth-Table of NOR based S-R Latch

  input output
S R QT +1
0 0 QT
0 1 0
1 0 1
1 1 INVALID

 

 

Question No: 28    ( Marks: 2 )

 

Two state assignments are given in the table below. Identify which state assignment is best and why?

 

States State assignment 1 State assignment 2
A 00 00
B 01 01
C 11 10
D 10 11

 

 Ans:

State assignment 2 is best assignment… it Minimizes the number of state variables that don’t change in a group of related states

Question No: 29    ( Marks: 2 )

 Write down at least two functions of a register.

 Ans:

1.      Registers are operating as a coherent unit to hold and generate data.

2.      registers functions also include configuration and start-up of certain features, especially during initialization, bufferstorage e.g. video memory for graphics cards, input/output (I/O) of different kinds,

 

Question No: 30    ( Marks: 2 )

 Define quantization process.

Ans:

The process by which we can convert an analogue signal into digital signal (code) is known as quantization process.

 

Question No: 31    ( Marks: 3 )

 How can we calculate the frequency of an unknown signal?

 

Ans:

The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval.

 

 

Question No: 32    ( Marks: 3 )

 Given the following statement used in PLD programming:

Y PIN 23 ISTYPE ‘com’;

Explain what does this statement mean?

 

Ans:

The Y variable is a ‘Combinational’ output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement

 

 

 

Question No: 33    ( Marks: 3 )

 Explain dynamic RAM in your own words.

 Ans:

Dram use latch to store a single bit of information. The main drawback of it id the discharge of capacitor over a period of time. Here four gates are used in making a single latch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged

Through a refresh cycle.

 Question No: 34    ( Marks: 5 )

 You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine.

 PresentState NextState
Q2 Q1 Q0 Q2 Q1 Q0
0 1 1 1 1 1
1 1 1 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
1 0 0 1 1 0
1 1 0 0 1 1

Question No: 35    ( Marks: 5 )

 Explain Memory Select or Enable Signals

Memory Select or Enable Signal:

  There are more than one memory chips to store program

Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously .

The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

 Question No: 36    ( Marks: 5 )

 Performance characteristics of D/A converters are determined by five parameters. Name them.

Ans:                          

Performances characteristics of D/A converters are determined by five parameters are as follow:

  1. 1.               Accuracy
  2. 2.               Setting time
  3. 3.               Monotonicity
  4. 4.               Linearity
  5. 5.               Resolution

FINALTERM  EXAMINATION

Spring 2010

CS302- Digital Logic Design (Session – 1)

 

Time: 90 min

arks: 58

 Question No: 1    ( Marks: 1 )    – Please choose one

“A + B = B + A”   is __________

► Demorgan’s Law

► Distributive Law

► Commutative Law

► Associative Law

Question No: 2    ( Marks: 1 )    – Please choose one

 The diagram given below represents __________

 

► Demorgans law

► Associative law

► Product of sum form

► Sum of product form

Question No: 3    ( Marks: 1 )    – Please choose one

Following is standard POS expression

 

► True

► False

Question No: 4    ( Marks: 1 )    – Please choose one

 An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______

► Using a single comparator

► Using Iterative Circuit based Comparators

► Connecting comparators in vertical hierarchy

► Extra logic gates are always required.

Question No: 5    ( Marks: 1 )    – Please choose one

 Demultiplexer is also called

► Data selector

► Data router

► Data distributor

► Data encoder

Question No: 6    ( Marks: 1 )    – Please choose one

 The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

► Doesn’t have an invalid state

► Sets to clear when both J = 0 and K = 0

► It does not show transition on change in pulse

► It does not accept asynchronous inputs

Question No: 7    ( Marks: 1 )    – Please choose one

A positive edge-triggered flip-flop changes its state when   ________________

► Low-to-high transition of clock

► High-to-low transition of clock

► Enable input (EN) is set

► Preset input (PRE) is set

Question No: 8    ( Marks: 1 )    – Please choose one

 A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

► 10 mW

► 25 mW

► 64 mW

► 1024

Question No: 9    ( Marks: 1 )    – Please choose one

 ____________ counters as the name indicates are not triggered simultaneously.

► Asynchronous

► Synchronous

► Positive-Edge triggered

► Negative-Edge triggered

Question No: 10    ( Marks: 1 )    – Please choose one

74HC163 has two enable input pins which are _______ and _________

► ENP, ENT

► ENI, ENC

► ENP, ENC

► ENT, ENI

Question No: 11    ( Marks: 1 )    – Please choose one

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

► Mod-6, Mod-10

► Mod-50, Mod-10

► Mod-10, Mod-50

► Mod-50, Mod-6

Question No: 12    ( Marks: 1 )    – Please choose one

 In a state diagram, the transition from a current state to the next state is determined by

► Current state and the inputs

► Current state and outputs

► Previous state and inputs

► Previous state and outputs

Question No: 13    ( Marks: 1 )    – Please choose one

A synchronous decade counter will have _______ flip-flops

► 3

► 4

► 7

► 10

Question No: 14    ( Marks: 1 )    – Please choose one

 ________ is used to minimize the possible no. of states of a circuit.

► State assignment

► State reduction

► Next state table

► State diagram

Question No: 15    ( Marks: 1 )    – Please choose one

A multiplexer with a register circuit converts _________

► Serial data to parallel

► Parallel data to serial

► Serial data to serial

► Parallel data to parallel

Question No: 16    ( Marks: 1 )    – Please choose one

 The alternate solution for a demultiplexer-register combination circuit is _________

► Parallel in / Serial out shift register

► Serial in / Parallel out shift register

► Parallel in / Parallel out shift register

► Serial in / Serial Out shift register

Question No: 17    ( Marks: 1 )    – Please choose one

 A GAL is essentially a ________.

► Non-reprogrammable PAL

► PAL that is programmed only by the manufacturer

► Very large PAL

► Reprogrammable PAL

Question No: 18    ( Marks: 1 )    – Please choose one

The output of this circuit is always ________.

 

 

► 1

► 0

► A

Question No: 19    ( Marks: 1 )    – Please choose one

DRAM stands for __________

 

 

► Dynamic RAM

► Data RAM

► Demoduler RAM

► None of given options

Question No: 20    ( Marks: 1 )    – Please choose one

in ____________, all the columns in the same row are either read or written.

 

 

► Sequential Access

► MOS Access

► FAST Mode Page Access

► None of given options

Question No: 21    ( Marks: 1 )    – Please choose one

FIFO is an acronym for  __________

► First In, First Out

► Fly in, Fly Out

► Fast in, Fast Out

► None of given options

Question No: 22    ( Marks: 1 )    – Please choose one

 In order to synchronize two devices that consume and produce data at different rates, we can use _________

► Read Only Memory

► Fist In First Out Memory

► Flash Memory

► Fast Page Access Mode Memory

Question No: 23    ( Marks: 1 )    – Please choose one

 A frequency counter ______________

► Counts pulse width

► Counts no. of clock pulses in 1 second

► Counts high and low range of given clock pulse

► None of given options

 

Question No: 24    ( Marks: 1 )    – Please choose one

The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2)

► 2n   (n multiplied by 2)

► 2n   (2 raise to power n)

► n  (n raise to power 2)

Question No: 25    ( Marks: 1 )    – Please choose one

Stack is an acronym for _________

► FIFO memory

► LIFO memory

► Flash Memory

► Bust Flash Memory

Question No: 26    ( Marks: 1 )    – Please choose one

The 4-bit 2’s complement representation of “+5” is _____________

► 1010

► 1110

► 1011

► 0101

Question No: 27    ( Marks: 2 )

Explain the erase operation in context of Flash Memory.

 

 

Question No: 28    ( Marks: 2 )

Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? 

 

 

 

Question No: 29    ( Marks: 2 )

Some of the counters (e.g. 74HC163) are called pre-set counters. why?

 

 

 

Question No: 30    ( Marks: 2 )

 How many bytes will be there in 32 K x 8 memory?

 

 

 

 

Question No: 31    ( Marks: 3 )

Differentiate between truth table and next-state table                   

 

 

 

 

Question No: 32    ( Marks: 3 )

Name the three types of errors Analogue to Digital converters exhibit during their conversion operation.

 

 

 

 

Question No: 33    ( Marks: 3 )

 How can a serial in/parallel out register be used as a serial in/serial out register?

 

 

Question No: 34    ( Marks: 5 )

Explain the implementation of First In First Out (FIFO) Memory by using RAM.

 

 

 

 

 

 

 

 

 

Question No: 35    ( Marks: 5 )

Explain memory read operation with the help of an example

 

 

 

 

 

 

 

 

 

 

 

Question No: 36    ( Marks: 5 )

Explain the next-state table with the help of a table for any sequential circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

MIDTERM  EXAMINATION

Spring 2010

CS302- Digital Logic Design

Time: 90 min

Marks: 58

Question No: 1    ( Marks: 1 )    – Please choose one

 A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

► 1

► 2

► 4

► 8

Question No: 2    ( Marks: 1 )    – Please choose one

 A frequency counter ______________

► Counts pulse width

► Counts no. of clock pulses in 1 second

► Counts high and low range of given clock pulse

► None of given options

 Question No: 3    ( Marks: 1 )    – Please choose one

 In a sequential circuit the next state is determined by ________ and _______

► State variable, current state

► Current state, flip-flop output

► Current state and external input

► Input and clock signal applied

 Question No: 4    ( Marks: 1 )    – Please choose one

 The divide-by-60 counter in digital clock is implemented by using two cascading counters:

► Mod-6, Mod-10

► Mod-50, Mod-10

► Mod-10, Mod-50

► Mod-50, Mod-6

Question No: 5    ( Marks: 1 )    – Please choose one

 In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.

► True

► False

Question No: 6    ( Marks: 1 )    – Please choose one

 Flip flops are also called _____________

► Bi-stable dualvibrators

► Bi-stable transformer

► Bi-stable multivibrators

► Bi-stable singlevibrators

Question No: 7    ( Marks: 1 )    – Please choose one

 The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

► Set-up time

► Hold time

► Pulse Interval time

► Pulse Stability time (PST)

Question No: 8    ( Marks: 1 )    – Please choose one

74HC163 has two enable input pins which are _______ and _________

► ENP, ENT

► ENI, ENC

► ENP, ENC

► ENT, ENI

Question No: 9    ( Marks: 1 )    – Please choose one

 ____________ is said to occur when multiple internal variables change due to change in one input variable

► Clock Skew

► Race condition

► Hold delay

► Hold and Wait

Question No: 10    ( Marks: 1 )    – Please choose one

 Given the state diagram of an up/down counter, we can find ________

► The next state of a given present state

► The previous state of a given present state

► Both the next and previous states of a given state

► The state diagram shows only the inputs/outputs of a given states

Question No: 11    ( Marks: 1 )    – Please choose one

 The _____________ input overrides the ________ input

► Asynchronous, synchronous

► Synchronous, asynchronous

► Preset input (PRE), Clear input (CLR)

► Clear input (CLR), Preset input (PRE)

Question No: 12    ( Marks: 1 )    – Please choose one

 A logic circuit with an output   consists of ________.

► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter

► two AND gates, one OR gate, two inverters

► two AND gates, one OR gate

Question No: 13    ( Marks: 1 )    – Please choose one

A decade counter is __________.

► Mod-3 counter

► Mod-5 counter

► Mod-8 counter

► Mod-10 counter

Question No: 14    ( Marks: 1 )    – Please choose one

 In asynchronous transmission when the transmission line is idle, _________

► It is set to logic low

► It is set to logic high

► Remains in previous state

► State of transmission line is not used to start transmission

Question No: 15    ( Marks: 1 )    – Please choose one

 A Nibble consists of _____ bits

► 2

► 4

► 8

► 16

Question No: 16    ( Marks: 1 )    – Please choose one

 The output of this circuit is always ________.

 

► 1

► 0

► A

Question No: 17    ( Marks: 1 )    – Please choose one

 Excess-8 code assigns _______ to “-8”

► 1110

► 1100

► 1000

► 0000

Question No: 18    ( Marks: 1 )    – Please choose one

 The voltage gain of the Inverting Amplifier is given by the relation ________

► Vout / Vin = – R/ Ri

► Vout / Rf = – Vin / Ri

► R/ Vin = – R/ Vout

► R/ Vin =   R/ Vout

Question No: 19    ( Marks: 1 )    – Please choose one

 LUT is acronym for ________

► Look Up Table

► Local User Terminal

► Least Upper Time Period

► None of given options

Question No: 20    ( Marks: 1 )    – Please choose one

 DRAM stands for __________

► Dynamic RAM

► Data RAM

► Demoduler RAM

► None of given options

Question No: 21    ( Marks: 1 )    – Please choose one

 The three fundamental gates are ___________

► AND, NAND, XOR

► OR, AND, NAND

► NOT, NOR, XOR

► NOT, OR, AND

Question No: 22    ( Marks: 1 )    – Please choose one

 

Which of the following statement is true regarding above block diagram ?

► Triggering takes place on the negative-going edge of the CLK pulse

► Triggering takes place on the positive-going edge of the CLK pulse

► Triggering can take place anytime during the HIGH level of the CLK waveform

► Triggering can take place anytime during the LOW level of the CLK waveform

Question No: 23    ( Marks: 1 )    – Please choose one

The total amount of memory that is supported by any digital system depends upon ______
► The organization of memory

► The structure of memory

► The size of decoding unit

► The size of the address bus of the microprocessor

Question No: 24    ( Marks: 1 )    – Please choose one

 The expression F=A+B+C describes the operation of three bits _____ Gate.

► OR

► AND

► NOT

► NAND

Question No: 25    ( Marks: 1 )    – Please choose one

 Stack is an acronym for_________

► FIFO memory

► LIFO memory

► Flash Memory

► Bust Flash Memory

Question No: 26    ( Marks: 1 )    – Please choose one

 Addition of two octal numbers “36” and “71” results in ________

► 213

► 123

► 127

► 345

Question No: 27    ( Marks: 2 )

 Define quantization process.

 

 

 

 

Question No: 28    ( Marks: 2 )

 

Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? 

 

 

Question No: 29    ( Marks: 2 )

 

A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented

 

 

 

 

Question No: 30    ( Marks: 2 )

 

Suppose a 2 bit up-counter, having states “A, B, C, D”. Write down GOTO statements to show how present states change to next states.

 

 

Question No: 31    ( Marks: 3 )

 Name three Operations that can be performed on FLASH Memory

 

 

 

Question No: 32    ( Marks: 3 )

 Explain Rotate Right Operation of shift register with the help of diagram.

 

 

Question No: 33    ( Marks: 3 )

 

 

You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs.

 

 

 

Question No: 34    ( Marks: 5 )

 Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward.

Question No: 35    ( Marks: 5 )

 Differentiate between synchronous and asynchronous RAM.

 

 

Question No: 36    ( Marks: 5 )

 

Explain Memory Select or Enable Signals

 

 

 

FINALTERM  EXAMINATION

Spring 2010

CS302- Digital Logic Design (Session – 4)

Time: 90 min

Marks: 58

 

Question No: 1    ( Marks: 1 )    – Please choose one

 The ANSI/IEEE Standard 754 defines a __________Single-Precision Floating Point format for binary numbers.

► 8-bit

► 16-bit

       ► 32-bit

► 64-bit

Question No: 2    ( Marks: 1 )    – Please choose one

 The decimal “17” in BCD will be represented as _________

► 11101

► 11011

       ► 10111

► 11110

Question No: 3    ( Marks: 1 )    – Please choose one

 The basic building block for a logical circuit is _______

► A Flip-Flop

       ► A Logical Gate

► An Adder

► None of given options

Question No: 4    ( Marks: 1 )    – Please choose one

 The output of the expression F=A.B.C will be Logic ________ when A=1, B=0, C=1.

► Undefined

► One

       ► Zero

► No Output as input is invalid.

Question No: 5    ( Marks: 1 )    – Please choose one

 ________ is invalid number of cells in a single group formed by the adjacent cells in K-map

► 2

► 8

       ► 12

► 16

Question No: 6    ( Marks: 1 )    – Please choose one

 The PROM consists of a fixed non-programmable ____________ Gate array configured as a decoder.

       ► AND

► OR

► NOT

► XOR

Question No: 7    ( Marks: 1 )    – Please choose one

 ___________ is one of the examples of synchronous inputs.

       ► J-K input

► EN input

► Preset input (PRE)

► Clear Input (CLR)

Question No: 8    ( Marks: 1 )    – Please choose one

 ___________ is one of the examples of asynchronous inputs.

► J-K input

► S-R input

       ► D input

► Clear Input (CLR)

Question No: 9    ( Marks: 1 )    – Please choose one

 The _____________ input overrides the ________ input

► Asynchronous, synchronous

► Synchronous, asynchronous

► Preset input (PRE), Clear input (CLR)

► Clear input (CLR), Preset input (PRE)

Question No: 10    ( Marks: 1 )    – Please choose one

 __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.

► Race condition

       ► Clock Skew

► Ripple Effect

► None of given options

Question No: 11    ( Marks: 1 )    – Please choose one

 Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be ___________

► 0000

       ► 1101

► 1011

► 1111

Question No: 12    ( Marks: 1 )    – Please choose one

 In a state diagram, the transition from a current state to the next state is determined by

      ► Current state and the inputs

► Current state and outputs

► Previous state and inputs

► Previous state and outputs

Question No: 13    ( Marks: 1 )    – Please choose one

 ________ is used to minimize the possible no. of states of a circuit.

► State assignment

► State reduction

► Next state table

► State diagram

Question No: 14    ( Marks: 1 )    – Please choose one

 ________ is used to simplify the circuit that determines the next state.

► State diagram

► Next state table

► State reduction

► State assignment

Question No: 15    ( Marks: 1 )    – Please choose one

 The best state assignment tends to ___________.

► Maximizes the number of state variables that don’t change in a group of related states

       ► Minimizes the number of state variables that don’t change in a group of related states

► Minimize the equivalent states

► None of given options

Question No: 16    ( Marks: 1 )    – Please choose one

 The output of this circuit is always ________.

 

       ► 1

► 0

► A

Question No: 17    ( Marks: 1 )    – Please choose one

 A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

► 1

► 2

► 4

       ► 8

Question No: 18    ( Marks: 1 )    – Please choose one

 5-bit Johnson counter sequences through ____ states

► 7

► 10

► 32

       ► 25

Question No: 19    ( Marks: 1 )    – Please choose one

 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)

► 1100

► 0011

       ► 0000

► 1111

Question No: 20    ( Marks: 1 )    – Please choose one

 The address from which the data is read, is provided by _______

        ► Depends on circuitry

► None of given options

► RAM

 Microprocessor

Question No: 21    ( Marks: 1 )    – Please choose one

 FIFO is an acronym for __________

► First In, First Out

► Fly in, Fly Out

► Fast in, Fast Out

► None of given options

Question No: 22    ( Marks: 1 )    – Please choose one

 LUT is acronym for _________

        ► Look Up Table

► Local User Terminal

► Least Upper Time Period

► None of given options

Question No: 23    ( Marks: 1 )    – Please choose one

 The voltage gain of the Inverting Amplifier is given by the relation ________

       ► Vout / Vin = – R/ Ri

► Vout / Rf = – Vin / Ri

► R/ Vin = – R/ Vout

► R/ Vin =   R/ Vout

Question No: 24    ( Marks: 1 )    – Please choose one

 ______ of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output.

► Resolution

► Accuracy

► Quantization

► Missing Code

Question No: 25    ( Marks: 1 )    – Please choose one 

Above is the circuit diagram of _______.

► Asynchronous up-counter

► Asynchronous down-counter

       ► Synchronous up-counter

► Synchronous down-counter

Question No: 26    ( Marks: 1 )    – Please choose one

 The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2)

► 2n   (n multiplied by 2)

► 2n   (2 raise to power n)

► n  (n raise to power 2)

Question No: 27    ( Marks: 2 )

 Draw the Truth-Table of NOR based S-R Latch

  input output
S R QT +1
0 0 QT
0 1 0
1 0 1
1 1 INVALID

 

 

Question No: 28    ( Marks: 2 )

 

Two state assignments are given in the table below. Identify which state assignment is best and why?

 

States State assignment 1 State assignment 2
A 00 00
B 01 01
C 11 10
D 10 11

 

 Ans:

State assignment 2 is best assignment… it Minimizes the number of state variables that don’t change in a group of related states

Question No: 29    ( Marks: 2 )

 Write down at least two functions of a register.

 Ans:

1.      Registers are operating as a coherent unit to hold and generate data.

2.      registers functions also include configuration and start-up of certain features, especially during initialization, bufferstorage e.g. video memory for graphics cards, input/output (I/O) of different kinds,

 

Question No: 30    ( Marks: 2 )

 Define quantization process.

Ans:

The process by which we can convert an analogue signal into digital signal (code) is known as quantization process.

 

Question No: 31    ( Marks: 3 )

 How can we calculate the frequency of an unknown signal?

 

Ans:

The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval.

 

 

Question No: 32    ( Marks: 3 )

 Given the following statement used in PLD programming:

Y PIN 23 ISTYPE ‘com’;

Explain what does this statement mean?

 

Ans:

The Y variable is a ‘Combinational’ output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement

 

 

 

Question No: 33    ( Marks: 3 )

 Explain dynamic RAM in your own words.

 Ans:

Dram use latch to store a single bit of information. The main drawback of it id the discharge of capacitor over a period of time. Here four gates are used in making a single latch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged

Through a refresh cycle.

 Question No: 34    ( Marks: 5 )

 You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine.

 PresentState NextState
Q2 Q1 Q0 Q2 Q1 Q0
0 1 1 1 1 1
1 1 1 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
1 0 0 1 1 0
1 1 0 0 1 1

Question No: 35    ( Marks: 5 )

 Explain Memory Select or Enable Signals

Memory Select or Enable Signal:

  There are more than one memory chips to store program

Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously .

The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed.

 Question No: 36    ( Marks: 5 )

 Performance characteristics of D/A converters are determined by five parameters. Name them.

Ans:                          

Performances characteristics of D/A converters are determined by five parameters are as follow:

  1. 1.               Accuracy
  2. 2.               Setting time
  3. 3.               Monotonicity
  4. 4.               Linearity
  5. 5.               Resolution

FINALTERM  EXAMINATION

Spring 2010

CS302- Digital Logic Design (Session – 1)

 

Time: 90 min

arks: 58

 Question No: 1    ( Marks: 1 )    – Please choose one

“A + B = B + A”   is __________

► Demorgan’s Law

► Distributive Law

► Commutative Law

► Associative Law

Question No: 2    ( Marks: 1 )    – Please choose one

 The diagram given below represents __________

 

► Demorgans law

► Associative law

► Product of sum form

► Sum of product form

Question No: 3    ( Marks: 1 )    – Please choose one

Following is standard POS expression

 

► True

► False

Question No: 4    ( Marks: 1 )    – Please choose one

 An alternate method of implementing Comparators which allows the Comparators to be easily cascaded without the need for extra logic gates is _______

► Using a single comparator

► Using Iterative Circuit based Comparators

► Connecting comparators in vertical hierarchy

► Extra logic gates are always required.

Question No: 5    ( Marks: 1 )    – Please choose one

 Demultiplexer is also called

► Data selector

► Data router

► Data distributor

► Data encoder

Question No: 6    ( Marks: 1 )    – Please choose one

 The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________

► Doesn’t have an invalid state

► Sets to clear when both J = 0 and K = 0

► It does not show transition on change in pulse

► It does not accept asynchronous inputs

Question No: 7    ( Marks: 1 )    – Please choose one

A positive edge-triggered flip-flop changes its state when   ________________

► Low-to-high transition of clock

► High-to-low transition of clock

► Enable input (EN) is set

► Preset input (PRE) is set

Question No: 8    ( Marks: 1 )    – Please choose one

 A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

► 10 mW

► 25 mW

► 64 mW

► 1024

Question No: 9    ( Marks: 1 )    – Please choose one

 ____________ counters as the name indicates are not triggered simultaneously.

► Asynchronous

► Synchronous

► Positive-Edge triggered

► Negative-Edge triggered

Question No: 10    ( Marks: 1 )    – Please choose one

74HC163 has two enable input pins which are _______ and _________

► ENP, ENT

► ENI, ENC

► ENP, ENC

► ENT, ENI

Question No: 11    ( Marks: 1 )    – Please choose one

The divide-by-60 counter in digital clock is implemented by using two cascading counters:

► Mod-6, Mod-10

► Mod-50, Mod-10

► Mod-10, Mod-50

► Mod-50, Mod-6

Question No: 12    ( Marks: 1 )    – Please choose one

 In a state diagram, the transition from a current state to the next state is determined by

► Current state and the inputs

► Current state and outputs

► Previous state and inputs

► Previous state and outputs

Question No: 13    ( Marks: 1 )    – Please choose one

A synchronous decade counter will have _______ flip-flops

► 3

► 4

► 7

► 10

Question No: 14    ( Marks: 1 )    – Please choose one

 ________ is used to minimize the possible no. of states of a circuit.

► State assignment

► State reduction

► Next state table

► State diagram

Question No: 15    ( Marks: 1 )    – Please choose one

A multiplexer with a register circuit converts _________

► Serial data to parallel

► Parallel data to serial

► Serial data to serial

► Parallel data to parallel

Question No: 16    ( Marks: 1 )    – Please choose one

 The alternate solution for a demultiplexer-register combination circuit is _________

► Parallel in / Serial out shift register

► Serial in / Parallel out shift register

► Parallel in / Parallel out shift register

► Serial in / Serial Out shift register

Question No: 17    ( Marks: 1 )    – Please choose one

 A GAL is essentially a ________.

► Non-reprogrammable PAL

► PAL that is programmed only by the manufacturer

► Very large PAL

► Reprogrammable PAL

Question No: 18    ( Marks: 1 )    – Please choose one

The output of this circuit is always ________.

 

 

► 1

► 0

► A

Question No: 19    ( Marks: 1 )    – Please choose one

DRAM stands for __________

 

 

► Dynamic RAM

► Data RAM

► Demoduler RAM

► None of given options

Question No: 20    ( Marks: 1 )    – Please choose one

in ____________, all the columns in the same row are either read or written.

 

 

► Sequential Access

► MOS Access

► FAST Mode Page Access

► None of given options

Question No: 21    ( Marks: 1 )    – Please choose one

FIFO is an acronym for  __________

► First In, First Out

► Fly in, Fly Out

► Fast in, Fast Out

► None of given options

Question No: 22    ( Marks: 1 )    – Please choose one

 In order to synchronize two devices that consume and produce data at different rates, we can use _________

► Read Only Memory

► Fist In First Out Memory

► Flash Memory

► Fast Page Access Mode Memory

Question No: 23    ( Marks: 1 )    – Please choose one

 A frequency counter ______________

► Counts pulse width

► Counts no. of clock pulses in 1 second

► Counts high and low range of given clock pulse

► None of given options

 

Question No: 24    ( Marks: 1 )    – Please choose one

The sequence of states that are implemented by a n-bit Johnson counter is

► n+2 (n plus 2)

► 2n   (n multiplied by 2)

► 2n   (2 raise to power n)

► n  (n raise to power 2)

Question No: 25    ( Marks: 1 )    – Please choose one

Stack is an acronym for _________

► FIFO memory

► LIFO memory

► Flash Memory

► Bust Flash Memory

Question No: 26    ( Marks: 1 )    – Please choose one

The 4-bit 2’s complement representation of “+5” is _____________

► 1010

► 1110

► 1011

► 0101

Question No: 27    ( Marks: 2 )

Explain the erase operation in context of Flash Memory.

 

 

Question No: 28    ( Marks: 2 )

Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? 

 

 

 

Question No: 29    ( Marks: 2 )

Some of the counters (e.g. 74HC163) are called pre-set counters. why?

 

 

 

Question No: 30    ( Marks: 2 )

 How many bytes will be there in 32 K x 8 memory?

 

 

 

 

Question No: 31    ( Marks: 3 )

Differentiate between truth table and next-state table                   

 

 

 

 

Question No: 32    ( Marks: 3 )

Name the three types of errors Analogue to Digital converters exhibit during their conversion operation.

 

 

 

 

Question No: 33    ( Marks: 3 )

 How can a serial in/parallel out register be used as a serial in/serial out register?

 

 

Question No: 34    ( Marks: 5 )

Explain the implementation of First In First Out (FIFO) Memory by using RAM.

 

 

 

 

 

 

 

 

 

Question No: 35    ( Marks: 5 )

Explain memory read operation with the help of an example

 

 

 

 

 

 

 

 

 

 

 

Question No: 36    ( Marks: 5 )

Explain the next-state table with the help of a table for any sequential circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

VU CS302- Digital Logic Design MIDTERM Solved/Unsolved Papers Spring 2010

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