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Posts Tagged ‘VU. cs302-.Digital. Logic. Design. midterm .examination .spring.007’

VU cs302-Digital Logic Design midterm examination spring 2007

.

Marks

Question

Marks

11 12

Question No: 1

( Marks: 2 )

– Please choose one

What is the decimal value of the terminal count of a 4-bit binary counter?

► 10

► 12

► 15

► 16

Question No: 2

( Marks: 2 )

– Please choose one

The 1’s complement of 10110111 is __________.

► 10110111

► 01001011

► 01101011

► 01001000

Question No: 3

( Marks: 2 )

– Please choose one

To serially shift a byte of data into a shift register, there must be?

► One clock pulse

► One load pulse.

► Eight clock pulses.

► One clock pulse for each 1 in the data.

.

Question No: 4

( Marks: 2 )

– Please choose one

What is the difference between a D latch and a D flip-flop?

.

► The D latch has a clock input.

► The D flip-flop has an enable input.

► The D latch is used for faster operation.

► The D flip-flop has a clock input.

Question No: 5

( Marks: 2 )

– Please choose one

For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will

______ if the clock goes HIGH.

► toggle

► set

► reset

► not change

Question No: 6

( Marks: 12 )

Draw the circuit diagram and truth table of the following equation.

F ( x, y, z)

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